MicroSim Newsletter - April 1997

Memory Devices, Timing Models, and Hierarchical Blocks

By Arnold Motley



Designers who use memory devices must be familiar with their setup and operation. Today memory devices are an integral part of not only personal computer systems but many other electrical devices as well. This article will demonstrate how to set up and simulate a circuit that uses a Random Access Memory (RAM) device. This article will also show how to include user-defined timing models and the simulation to help generate more realistic results. Finally the memory controller portion of the circuit will be converted to a hierarchical block to demonstrate the usefulness of hierarchical design. Table 1 contains a list of the terminology used in this article and their definitions.

Table 1: Terminology and Definitions
Terminology Definition
7404 Inverter
7408 2 input AND gate
74f112 JK flip-flop
74161 4 bit asynchronous binary counter
Ram8kX8break 8 bit 64k memory device
DAC8break 8 bit digital to analog converter
ADC8break 8 bit analog to digital converter
we Write Enable line of the RAM device
re Read Enable line of the RAM device
a0-a12 address lines
r0-r7 read data lines
w0-w7 write data lines
0000h hexi-decimal value of 0
0000b binary value of 0
block hierarchical block
ns nano-second
ms micro-second
ms mill-second
vp-p peak to peak voltage

Circuit Description

Figure 1 illustrates an example of what memory devices are used for. The purpose of the circuit will be to take a 1 Hz, 1 Vp-p, 2.5 volt offset sine wave and convert it into a digital signal. The digital signal will then be written to a RAM device which will save approximately 2.5 seconds worth of the signal. At that point, the supporting circuitry will convert the RAM configuration from a write mode to a read mode. The memory device will then send the saved data to a DAC device for 2.5 seconds and the DAC part will convert the signal from the RAM back into an analog voltage which will be dropped across an output resistor. The frequencies, duty cycles, and time delays for all of the sources have been calculated and set to ensure the RAM part will be set to the read and write cycle modes at the proper times.

Figure 1 - Top-level schematic using memory devices (memory_1.sch)

Circuit Operation

The Clear Signal and the Proper Signal Relationship

The circuit will first convert the analog 1 Hz, 1 Vp-p, 2.5 volt offset sine wave from V1 (shown at the far right of the schematic) into a digital wave form. This is done by U26, the ADC8break part. The 8-bit digital output from U26 is then applied to the write inputs (w0-w7*) of the RAM device, U10.

*signal names and file names will be in italics

In order to set up the RAM device in a write mode (data sent to and stored in the RAM device), the supporting circuitry must provide a repetitive we pulse. The discussion that follows will describe the supporting circuitry necessary to perform this task.

The three binary counters in Figure 1 (U1, U2, U3) are used in a cascading manner to provide the address values for the RAM device. The clear signal (clr) from DSTM1 is used to perform two functions: it clears the three counters and the JK flip-flops (U4A,U5A, U6A). The second function the clear signal performs is to ensure that the circuit components are in a known state at the time of power-up. Once the clear signal has reset the counters, the starting address location is set to a hex value of 0. The clear signal also ensures that logic 0's are applied to the re and we inputs of the RAM device. This keeps the RAM device out of the read and write modes. This is done by setting the re_0 and we_0 to logic 0's at the inputs for both the U13A and U14A parts.

Once the clear signal is removed, logic 1's are placed on both inputs of the U8A device. This in turn places a logic 1 on the clr_1 signal of pin 3 on U6A. This will enable the we_0 signal to cycle at the same frequency as the clock_1 signal. When both the we_0 and cnvrt signals are high, this condition will generate the we signal going to the RAM device via U14A pin 3. At the time the we signal is generated, that portion of the analog signal which is present on the write lines of U10 will be saved at the corresponding address locations of the RAM part. A certain relationship must be established between the address signals, the data that is being written to the RAM device, and the we signal.

The address line signals going to the RAM chip are first placed in a stable condition, then the data coming in is set, and finally the we signal is asserted. Once the data coming in is written, the three signals are removed in the reverse order that they were applied. In other words, the a1 address line pulse must encapsulate the we pulse while the write lines w0-w7 are stable during a write operation. If this relationship is maintained, there should be no errors generated. The a0 line is set to a permanent logic 0 because the counters have twelve address lines, while the RAM part has thirteen address lines. How the supporting logic generates the we pulses and then switches the RAM to a read mode will now be discussed.

The Supporting Logic

The clock_in signal feeds the clk pins of the three counters and the JK flip-flops. The delay time for the clock_in signal is set at 0.2 ms. This provides a reference time starting point for the circuit. The high time for the clock_in signal was set at 0.28125 ms and the low time was also set at 0.28125 ms. This provides a period of 0.5625 ms for the clock_in signal. The cycle time for the U1 counter is twice the clock_in period, or 1.125 ms. When U1 cycles to 1111b, it then resets to a binary value of 0000b and a high pulse is provided on the rco1 line. This causes U2 to count up by one. This process continues until U2 counts up and resets, and a high pulse is generated on the rco2 line. When U3 resets to 0000b from 1111b, the toggle line will send a high pulse to the JK inputs of U4A. This will cause the Q output of U4A to toggle from a logic 0 to a logic 1.

After the clear signal and prior to the first toggle pulse from U3, the RAM part will be in a write mode. Since the number 2 input of U8A was set to a logic 1 after the clear signal was removed, the logic 1 on the number 1 input pin will set the clr_1 signal on U8A pin 3 to a logic 1. This will remove the clear signal from the number 15 pin of the U6A JK flip-flop. With the high signal removed from pin 1 of U8A and the JK inputs of U6A placed at a logic 1, the Q output of U6A, we_0 , will cycle with every clock_1 pulse from V7.

The time delay of V7 was set at 0.4 ms to allow for the start-up and removal of the clear signal and to ensure the clock_1 signal was in sync with the address and data lines of U10. The high time for the clock_1 signal is 1 ms, and the low time is 35 ms, which provides a period of 36 ms. The we_0 signal will be a reflection of the clock_1 signal, and it will be sent to the number 1 input of U14A. The signal on the number 2 input of U14A is the cnvrt signal.

The cnvrt signal has a delay time of 0.4 ms. It also has a high time of 0.05 ms and a low time of 35.95 ms. This provides a period of 36 ms for the cnvrt signal. The high section of the cnvrt signal is set up to occur when the clock_1 signal is high. These two signals generate the we signal at pin 3 of U14A. Every time the we signal is high, it places the RAM part in a write mode. At this point, data on the write line signals, w0-w7, will be sent to the address location which is selected at that time by the three counters.

The supporting logic also provides this periodic we signal for approximately 2.5 seconds. To calculate the total time for the periodic we and re signals the following equation was used:


     = (high time for clock_1 x 2 x 212 + 0.2) seconds
     = (0.28125 ms x 2 x 212 + 0.2) seconds
     = 2.504 seconds

The high time for the clock_1 signal is multiplied by 2 to account for the entire period. The period is then multiplied by the time it takes all three clocks to cycle through and generate the toggle pulse on the RCO pin of U3. To calculate the time it takes to toggle U1, U2, and U3's RCO lines, the formula ab was used. Where a is the number of possible signal states per line, in this case two, either logic 1 or logic 0. The b is the number of counter outputs, four for each binary counter which gives a total of twelve. We add 0.2 because of the time delay in the clr signal.

While the time window available to generate the we signal is 2.504 seconds, the actual assertion of the we signal will be a reflection of the cnvrt signal. This implies that the series of we pulses will be approximately 0.05 ms in width and occur every 36 ms inside the 2.504 second window. The signal waveforms shown in Figure 2 show the relationships between the clock_in, clock, rco1, rco2, clr_1, clock_1, we_0, cnvrt, we, and the toggle signal.

Figure 2 - Relationships between clock and toggle signal.

After 2.504 seconds have elapsed, the toggle signal from U3 is asserted, and this changes the Q output on U4A from a logic 0 to a logic 1. This places the RAM device in a read mode. The entire process that generated the we signal is replaced by the re signal for another 2.504 seconds. After the first toggle pulse, the three counters reset to 0 for preparation of the read cycle. This sets the address lines back to their 0000h address. As the re signal is generated in a manner similar to that of the we signal, the RAM device places the data stored in its memory on the inputs of U11, the DAC8break part. The V5 source at the reference input (REF) of the DAC provides the maximum reference voltage level for the output signal across resistor R1. The input analog signal from V1 and the analog output voltage signal across R1 are shown in Figure 3. As Figure 3 shows, the RAM part did indeed store and then recall the sine wave signal.

Figure 3 - Input analog signal from V1 and analog output voltage signal across R1.

Timing Analysis

While this circuit shows how a memory device can be simulated with MicroSim PSpice, it is not entirely accurate. One aspect of successful simulation has been left out: the timing associated with each device in the circuit. In other words, up to this point the circuit and the output waveforms are reflecting an ideal circuit with no propagation delays or other timing parameters included. This section will demonstrate how timing parameters such as propagation delays, setup times, and hold times can be added to make the simulation react more like an actual circuit. Also, an error will be placed in the timing parameters on purpose to show how MicroSim PSpice detects and indicates this sort of problem. Although MicroSim PSpice has the ability to simulate many of the timing parameters associated with logic devices, only some of the parameters will be used for each device in this article for brevity. The MicroSim library "dig_io.lib" contains the full timing parameters for its models. These parameters were obtained from TI's data book.

The first step to modify the timing values is to obtain the propagation delay values from a logic data book. MicroSim PSpice will except timing parameters for the minimum (MN), typical (TY), and maximum (MX) values for each device. Once all of these values have been added to the part model, MicroSim PSpice provides the option to run all of the components in the circuit at either their MN, TY, or MX values. If a particular part or several different parts require that their timing parameters are simulated at a different level from the global setting, then these parameters can be set by double clicking the part and typing in the value of 1, 2, or 3 in the "MNTYMXDLY" attribute line. This feature will be discussed later in this article.

Table 2: Parameters and Values Used in Simulation
Part Parameter Description MN TY MX
re74F04 tplh propagation delay low to high 2.4ns 3.7ns 5ns
tphl propagation delay high to low 1.5ns 3.2ns 4.3ns
74F08 tplh propagation delay how to high 3ns 4.2ns 5.6ns
tphl propagation delay high to low 2.5 ns 4ns 5.3ns
74F112 thdclk hold time for JK after the clock 0 0 0
tpclkqlh time delay clock edge to q low to high 2ns 5ns 6.5ns
tpclkqhl tie delay clock edge to q high to low 2ns 5ns 6.5ns
tsudclk setup time JK to the clock 4ns 4ns 4ns
DAC8break tsw switching time change in data to analog out stable 0.8ms 1.6ms 2.5ms
RAM8Kxbreak tpadh delay address to read data lot to high 2.9ns 3.7ns 4.2ns
tpadl delay address to read data high to low 2.6ns 3.1ns 3.7ns
tsuaew minimum setup time address to write enable 2.3ns 3ns 3.6ns

Table 2 gives a description of the parameters used in the simulation and the value that was used for each. The values in the MN, TY, and MX columns are added to the model statements of the individual parts to allow for the addition of these user-defined timing parameters in the simulation. The definition for the 74F08 model before the user-specified timing parameters were added was:

.subckt 74F08-X  A B Y
+       optional: DPWR=$G_DPWR DGND=$G_DGND
+       params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+	A B   Y 

The following timing parameters were added before the .ends statement:

.model D_F08 ugate
*Propagation delay low to high
+ tplhmn=3n tplhty=4.2n tplhmx=5.6n
*Propagation delay high to low
+ tphlmn=2.5n tphlty=4n tphlmx=5.3n

The ".model D_F08-X ugate" was added before the ".ends" statement. D_F08-X is the model name (as shown in the first definition), and is normally listed right before the I/O model name. The ugate describes the gate type. For example, low-level digital devices such as gates use the "ugate" type. If the part was a JK Flip-Flop, then the gate type would be "ueff" as described below.

A remark statement has been added to describe the first set of timing parameters. To create a remark statement, an asterisk is placed at the beginning of the line. It reads, "Propagation delay low to high", and the minimum, typical, and the maximum values have been listed. Following this line is another remark statement, and the parameters for the propagation delay from high to low are listed. Finally, the ".ends" statement completes the model entry. Below is the timing model for the JK flip-flops used in the circuit:

+	optional: DPWR=$G_DPWR DGND=$G_DGND
+	params: MNTYMXDLY=0 IO_LEVEL=0
+	J K   J_BUF K_BUF 
UB1 bufa(2) DPWR DGND
+	J_BUF K_BUF   J1 K1 
UB2 bufa(2) DPWR DGND
+	J_BUF K_BUF   J1 K1 
U1 jkff(1) DPWR DGND
.model D_F112_2 ueff
*Hold time for JK after the clock
+ thdclkmn=0 thdclkty=0 thdclkmx=0
*Time delay clock edge to q low to hi
+ tpclkqlhmn=2n tpclkqlhty=5n tpclkqlhmx=6.5n
*Time delay clock edge to q hi to low
+ tpclkqhlmn=2n tpclkqhlty=5n tpclkqhlmx=6.5n
*Setup time JK to clk
+ tsudclkmn=4n tsudclkty=4n tsudclkmx=4n

Similar timing entries are made for the rest of the devices. The counters did not have timing models added since the counter is basically modeled with flip-flops and logic gates, and these types have been shown.

Minimum, typical, and maximum values have been added for each of the timing models, and need to be selected in the Digital Options dialog. To set these values, in MicroSim Schematics choose Analysis/Setup, then click on Digital Setup. Three options will be shown: Timing Mode, Default A/D Interface, and Flip-flop Initialization. Under the Timing Mode sub-window are four options: Minimum, Typical, Maximum, Worst-case (Min/Max).

The option selected in the Timing Mode window sets the global timing for the circuit. For example, if a typical value of 2 was chosen, then all of the devices that had timing parameters in their models would have those parameters set to the typical values. If for some reason the designer would like to have the global parameter set for the "typical" value but would like one particular part or a group of parts set to the maximum values, this condition could also be simulated. To set the timing for individual devices to a different value from that of the global setting, the "MNTYMXDLY" value in the attribute window of the individual device must be set to the desired setting.

A value of 1 signifies a minimum value, a value of 2 signifies a typical value, and a value of 3 signifies a maximum value. As long as the device has a timing model defined, the "MNTYMXDLY" value for that device can be set to a value other than the global setting.

Since all of the timing parameters in the circuit are either s or ms and the clock frequency is in ns, there were no timing discrepancies. In order to show how MicroSim PSpice detects and reports timing discrepancies, one of the timing parameters was changed to create a timing hazard. Changing the "thdclk" parameter (which is the hold time for JK after the clock) for the U4A part from 0 s to 1 s creates a timing hazard.

After the simulation MicroSim PSpice notifies that a digital warning has occurred. The output file includes the set and measured values for the warning parameter (shown below). In this case the measured value was 19.8 ns while the set value was 1 s.

DIGITAL Message ID#1 (Warning)
HOLD Violation at time 2.5036062767s
	Device:	X_U4A.U1
	Clock:	clock_bar
	J:	X_U4A.JI
Minimum THDCLK = 1s
Measured J/CLOCK hold = 19.8ns

Advantages of Hierarchical Design

At this point the circuit is operating as planned, but a look at the circuit in Figure 1 shows that there is a fair amount of logic to understand. Circuits with more sophisticated functions and component design would be even more time consuming to understand. To overcome this problem, a designer can implement a hierarchical design. In this section the circuit in Figure 1 will be reduced by combining several of the components into a hierarchical block.

Hierarchical blocks are components which provide all of the function of the circuits they are replacing. For example, in Figure 1, all of the components to the left of the RAM part could be called the memory controller. For a top-level design scheme, the memory controller can be represented by a single part.

To start this process, a copy of the memory controller section of the circuit in Figure 1 is made by using the copy and paste function within MicroSim Schematics. Next, the four sources: DSTM1, DSTM2, V7, and cnvrt are removed from the copy of the memory controller. This is done because it is easier to change the source parameters when they are on the bottom level. If they were left in the hierarchical block, there would be no way to adjust their operating conditions unless the designer pushed inside the block.

After the sources have been removed, a copy of that portion of the circuit which will go into the hierarchical block is then saved as inside_1.sch (Figure 4). The next step in the procedure is to create the hierarchical block. This is done either by clicking on the toolbar icon or by selecting Block from the Draw menu. A window will prompt the user for a schematic to reference, in this case inside_1.sch is entered. Once the block is in place, the file is saved as package_1.sch.

Figure 4 - Hierarchical block "inside_1.sch"

A link has to be created between the circuit inside the block and the circuit outside of the block. This is accomplished by the hierarchical block pins. Pins on the left side of the block are considered to be inputs, and pins on the right side of the block are output pins. To accommodate the number of output pins, the block used in this design had to be enlarged. This was done with the following series of commands:


  1. Click on the hierarchical block to highlight it,
  2. Hold the Shift key,
  3. Right-click the mouse and move it to create the new desired size for the hierarchical block.

Now that the block has been resized, the pins for the block must be placed. Basically every signal line which must go from the inside to the outside of the block must have a pin on the hierarchical block. In this case each of the thirteen address lines going to the memory device must have a pin as well as the four source pins. To create the pins on the block level, a new wire must be started where the new pin will be placed on the block. The wire is drawn such that it terminates on the block. A pin is automatically created (and numbered where the wire meets the block). The pins can be renumbered or renamed by double-clicking on the pin and then typing in the change. Pins P1 through P19 (Figure 5) were created in this manner. This creates the link on the outside of the block, and to create the link for the circuit on the inside of the block, the interface port must be used.

Figure 5 - final_1.sch schematic

To create the link on the inside of the block, highlight the block and then press F2 or select Push from the Navigate menu to push into the block. An "interface" port is then placed on each line which will go to the outside of the block. Once the interface ports are placed on the inside of the block, their labels must be changed to reflect the corresponding pin names that are on the block level. The schematic in Figure 4, inside_1.sch, shows the circuitry contained inside the block.

Once the hierarchical block is completed both inside and out, the block can be used by any circuit as if it were just another part in the MicroSim PSpice library. For example, the memory controller section is copied from the original circuit in Figure 1 (not including the four sources). The memory controller block is then copied from the package_1.sch to a new file called final_1.sch. The remainder of the original circuit which includes the RAM part, the DAC and the ADC are also copied to the final_1.sch file.

The final_1.sch schematic is shown in Figure 5. Notice that the voltage sources have been reconnected to the left side of the block. If the final_1.sch circuit is now simulated, the results will be the same as the results from the memory_1.sch circuit. How the hierarchical block simplifies the look of the circuit design and makes it easier to follow can be seen when the final_1.sch circuit is compared to the memory_1.sch. Hierarchical blocks can be made to include as much or as little of the circuit as desired.

The hierarchical block has reduced the original circuit from about 17 components down to about five components, yet the original function remains the same. This block could also be converted into a permanent symbol which will allow this design or other designs to access it directly from the library in the same manner as other library components.

This article has shown some useful examples of how to use memory devices, how to include timing models, and how to use hierarchical blocks.

Arnold Motley works for a computer company in North Carolina. He lives there with his wife Yvonne and their three children.